1. Field of the Invention
The present invention relates to a circuit for outputting clock signal with a predetermined frequency regardless of variations in the environmental temperature or voltage of a direct power source which supplies power to the circuit.
2. Description of the Related Art
Clock signal guaranteed to have a fixed frequency are required to enable accurate timing measurements. To this end, development of a circuit for outputting clock signal with the fixed frequency is under way. This type of clock signal output circuit is required to be capable of maintaining oscillating frequency of clock signal at constant level.
An oscillating circuit for oscillating clock signal that is referred to as a ring oscillator is known. FIG. 3a shows a conventional ring oscillator circuit 30 (one example of the clock signal output circuit) that has been improved to stabilize oscillating frequency. This ring oscillator circuit 30 is disclosed in Japanese Patent Application Laid-Open Publication No. 2003-283305. The ring oscillator circuit 30 comprises a first terminal 6 connected to a positive pole of a direct power source 12, a second terminal 7 connected to a negative pole of the direct power source 12, and a third terminal 8 for outputting clock signal. Between the first terminal 6 and the second terminal 7 are connected in parallel an odd number (3 pairs in FIG. 3a) of 1st pair of transistors. 2nd pair of transistors, and 3rd pair of transistors. In the 1st pair of transistors 1, an upper transistor 1a and a lower transistor 1b are connected in series. In the 2nd pair of transistors 2, an upper transistor 2a and a lower transistor 2b are connected in series. In the 3rd pair of transistors 3, an upper transistor 3a and a lower transistor 3b are connected in series. A midpoint 1d between the upper transistor 1a and the lower transistor 1b of the 1st pair of transistors 1 is connected to a gate of the lower transistor 2b of the 2nd pair of transistors 2. A midpoint 2d between the upper transistor 2a and the lower transistor 2b of the 2nd pair of transistors 2 is connected to a gate of the lower transistor 3b of the 3rd pair of transistors 3. A midpoint 3d of the upper transistor 3a and the lower transistor 3b of the 3rd pair of transistors 3 is connected to a gate of the lower transistor 1b of the 1st pair of transistors 1. A capacitor 1c is inserted between the gate of the lower transistor 1b of the 1st pair of transistors 1 and the second terminal 7. A capacitor 2c is inserted between the gate of the lower transistor 2b of the 2nd pair of transistors 2 and the second terminal 7. A capacitor 3c is inserted between the lower transistor 3b of the 3rd pair of transistors 3 and the second terminal 7. The third terminal 8 is connected to a midpoint 3e of the upper transistor 3a and the lower transistor 3b of the 3rd pair of transistors 3.
All of the upper transistors 1a, 2a, 3a are of a p-type transistor and have same specification. All of the lower transistors 1b, 2b, 3b are of a n-type transistor and have same specification. The capacitors 1c, 2c, 3c have same specification.
The ring oscillator circuit 30 comprises a constant current circuit 29 that maintains at constant level current IP flowing through the upper transistors 1a, 2a, and 3a even when supply voltage of the direct power source 12 fluctuates. The constant current circuit 29 comprises an additional upper transistor 6a, and a constant current regulator 20. The additional upper transistor 6a and the constant current regulator 20 are connected in series between the first terminal 6 and the second terminal 7. In the additional upper transistor 6a, a gate and a drain are connected. A midpoint between the additional upper transistor 6a and the constant current regulator 20 is connected to each gate of the upper transistors 1a, 2a, 3a. 
As shown in FIG. 3b and FIG. 3c, the ring oscillator circuit 30 outputs clock signal (shown in FIG. 3c) that repeat on/off inversions with certain frequency to the third terminal 8, while gate-on voltage (shown in FIG. 3b) is being inputted to the gate of the additional upper transistor 6a from a terminal 9.
FIG. 4 shows a relationship of voltage of the capacitors 1c, 2c, 3c and temporal change. VT represents gate voltage (threshold voltage) when the lower transistors (n-type transistors) 1b, 2b, 3b are turned on. tr represents time taken to charge the discharged capacitors 1c, 2c, 3c to the threshold voltage VT. tf represents time since the charged capacitors 1c, 2c, 3c begin to discharge till voltage of the capacitors 1c, 2c, 3c drops to the threshold voltage VT. VH represents voltage when each of the capacitors 1c, 2c, 3c begins to discharge.
The ring oscillator circuit 30 operates as described below. For instance, immediately before timing t0, only the transistor 2b is on, and the transistor 1b and the transistor 3b are off. As the transistor 2b is on, the capacitor 3c is discharged. As the transistor 3b is off, the capacitor 1c is being charged. As the transistor 1b is off, the capacitor 2c is being charged.
At timing t0, when voltage of the capacitor 1c becomes equal to the threshold voltage VT of the transistor 1b, the transistor 1b is turned on. As a result, the capacitor 2c begins to discharge. The transistor 2b will be turned off tf time after timing t0. When the transistor 2b is turned off, the capacitor 3c begins to charge.
At timing t1, when voltage of the capacitor 3c becomes equal to the threshold voltage VT of the transistor 3b, the transistor 3b is turned on. As a result, the capacitor 1c begins to discharge. The transistor 1b will be turned off tf time after the timing t1. When the transistor 1b is turned off, the capacitor 2c begins to charge.
At timing t2, when voltage of the capacitor 2c becomes equal to the threshold voltage VT, of the transistor 2b the transistor 2b is turned on. As a result, the capacitor 3c begins to discharge. The transistor 3b will be turned off tf time after the timing t2. When the transistor 3b is turned off, the capacitor 1c begins to discharge.
At timing t3, when voltage of the capacitor 1c becomes equal to the threshold voltage VT of the transistor 1b, the transistor 1b is turned on. As a result, the capacitor 2c begins to discharge. The transistor 2b will be turned off tf time after the timing t3. When the transistor 2b is turned off, the capacitor 3c begins to charge. This event is equal to that at timing t0. Consequently same phenomenon occurs at timings t4 and t1, and at timing t5 and t2.
With the ring oscillator circuit 30, the transistor 1b repeats action of turning on at the timing t0 and turning off at t1+tf. The transistor 2b repeats action of turning on at timing t2 and turning off at t3+tf. The transistor 3b repeats action of turning on at timing t1 and turning off at t2+tf.
With the ring oscillator circuit 30 of FIG. 3a, the constant current regulator 20 maintains current flowing through the upper transistor 6a at constant current IP.
In the ring oscillator circuit 30 of FIG. 3a, the constant current circuit 29 comprising the additional upper transistor 6a and the constant current regulator 20 configures a current mirror circuit to the 1st pair of transistors 1. As a result, gate voltage to be applied to the additional upper transistor 6a is equal to gate voltage to be applied to the upper transistor 1a, current IP flowing through the additional upper transistor 6a is equal to current flowing through the upper transistor 1a. Similarly, the constant current circuit 29 configures a current mirror circuit to the 2nd pair of transistors 2. Gate voltage to be applied to the additional upper transistor 6a is equal to gate voltage to be applied to the upper transistor 2a, and current IP flowing through the additional upper transistor 6a is equal to current flowing through the upper transistor 2a. In addition, the constant current circuit 29 configures a current mirror circuit to the 3rd pair of transistors 3. Gate voltage to be applied to the additional upper transistor 6a is equal to gate voltage to be applied to the upper transistor 3a, and current IP flowing through the additional upper transistor 6a is equal to current flowing through the upper transistor 3a. In the ring oscillator circuit 30 of FIG. 3a, voltage equal to the voltage to be applied to the gate of the additional upper transistor 6a is applied to gates of the respective upper transistors 1a, 2a, 3a. As a result, the current flowing through the respective upper transistors 1a, 2a, 3a is maintained at the constant current IP.
The vertical axis of FIG. 2 represents oscillating frequency, while the horizontal axis represents environmental temperature. Curves 21a, 21b, 21c show a relationship between oscillating frequency of the ring oscillator circuit 30 and the environmental temperatures. The curve 21a shows the case in which voltage of the direct current source 12 is 3.6 volts, the curve 21b shows the case that voltage of the direct current source 12 is 3.3 volts, and the curve 21c shows the case that voltage of the direct current source 12 is 3.0 volts. In the ring oscillator circuit 30 of FIG. 3a, even if the source voltage fluctuates, the oscillating frequency does not change much